The invention relates to the field of semiconductor process technology and in particular to the production of through-substrate vias (TSVs) using DRIE (Deep Reactive Ion Etching). TSVs provide electric interconnections between opposite main sides of a semiconductor device and are useful for many applications, especially in three-dimensional integration of integrated circuits, for example.
WO 2012/031845 A1 discloses a manufacturing method for semiconductor devices comprising a through-substrate via. A contact hole is formed through the intermetal dielectric and the semiconductor material of the substrate, and a contact area of a metal plane that faces the substrate is exposed in the contact hole. A metallization is applied to form a contact on the contact area and an interconnection penetrating the substrate to contact an opposite further contact area facing away from the substrate.
U.S. Pat. No. 5,501,893 A discloses a method of anisotropically etching silicon to provide laterally defined recess structures. Silicon is removed by plasma etching using a reactive etching gas. A polymer former contained in the plasma is then used to generate a polymer layer on the etched surface, which inhibits the etching process until the polymer is removed. The etching step and the polymerizing step are alternatingly repeated. This method is generally known in the art as Bosch process, after the assignee of the patent, and is also known as pulsed or time-multiplexed etching.
In the Bosch process a standard, essentially isotropic plasma etching is performed to etch a deep opening in silicon. The plasma may comprise SF6, sulfur hexafluoride, for instance. After a few seconds of etching, a chemically inert passivation layer is formed to protect the silicon surface from further attack, thus inhibiting further etching. The passivation layer is typically formed from a polymer former contained in the plasma and may comprise C4F8, octafluorocyclobutane, for instance. In a subsequent anisotropic etching step, the passivation layer is removed from the bottom of the opening while remaining on the sidewall, so that only the bottom of the opening is subsequently again exposed to the etchant.
The etching and polymerizing steps are alternatingly repeated, so that many small isotropic etching steps are performed, which yield an overall deep anisotropic etching. To etch through a 0.5 mm silicon wafer, for example, 100 to 1000 cycles of etching and polymerizing are performed. The sequence of polymer layers formed on the sidewall during consecutive etching and passivating cycles renders the sidewall undulated. When etching is completed, the sidewall of the opening comprises striations and a typical roughness. The cycle time can be adjusted: short cycles yield smoother walls, and long cycles yield a higher etch rate.